Conventional approaches to high voltage generation (both positive and negative) implement discrete pumps for each of the positive and negative requirements on a particular integrated circuit device. These separate pumps typically operate separately for erasing and programming. On-chip high voltage pumps based on simple voltage doubler techniques often suffer from inefficiencies due to body bias effects. These on-chip voltage requirements are typically in the +16v and -10v region. In multi-stage pumps, the latter stages are often transferring charge within MOS transistors under conditions of heavy body bias. This may result in the voltage increments produced by each of the stages tailing off significantly as the high voltages are reached. Specifically, and by way of example, in a conventional CMOS twin-well process with a P-substrate, only P-channel transistors can be used for negative voltage generation (&lt;VSS), otherwise forward-biased diodes would result. Consequently, the less the end-voltage (in relation to chip supplies) the more efficient the pump.